1. Technical Field
The present invention relates in general to data processing and, in particular, to resource allocation in a processor. Still more particularly, the present invention relates to a method and system for on-demand scratch register renaming in a processor.
2. Description of the Related Art
A typical superscalar microprocessor is a highly complex digital integrated circuit including, for example, one or more levels of cache memory for storing instructions and data, a number of execution units for executing instructions, instruction sequencing logic for retrieving instructions from memory and routing the instructions to the various execution units, and registers for storing operands and result data. Interspersed within and between these components are various queues, buffers and latches for temporarily buffering instructions, data and control information. As will be appreciated, at any one time the typical processor described above contains an enormous amount of state information, which can be defined as the aggregate of the instructions, data and control information present within the processor.
Many microprocessors implement microcode to break complex instructions into smaller operations (a.k.a. internal ops, or iops). To transfer data between iops, the prior art solution defines a small fixed number of General Purpose Registers (GPRs) as scratch registers (a.k.a. extended GPRs, or eGPRs) for use only by microcode. Scratch registers are storage locations dedicated to the storage of operands of microcode instructions. In order to have a compact instruction encoding, most processor instruction sets have a small set of special locations which can be directly named. These registers capable of being directly named are called rename registers, and are storage locations for a future state of an architected register. Register renaming refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations. One limiting performance factor in an out-of-order microprocessor design is the availability of GPR rename registers. Under the prior art, the total number of rename registers available is equal to the total number of physical registers less the number of logical registers defined for each thread, because the latest set of committed logical registers must be preserved for the possibility that speculative out-of-order instructions are flushed.
Speaking generically of the prior art, the relationship between available rename registers and physical registers is: Nrename=Nphysical−Nthreads*Nlogical. However, for the known solution—for a microprocessor performing out-of-order instructions with microcode (and thus scratch registers), the relationship becomes Nrename=Nphysical−Nthreads*(Nlogical+Nscratch). The result of the prior art solution is that, for a microprocessor with multiple threads, the number of renames available for computation can become significantly reduced, due in large measure to the prior-art solution for scratch register handling.